UDPi™ is located between the Instruction Fetcher and the Instruction Decoder. The GOTO location does not have to be in sequence. For example, an instruction in a non-UDPi™ device may be GOTO location 100 then GOTO location 200. Processors are normally sequential, but with UDPi™, the processor’s execution can be RANDOM.
The Instruction Decoder is modified with the use of UDPiCore security, creating the UDPi HardKey, which enables data to be translated to a useful form from its secured, uniquely scrambled format.
EPROM memory can be scrambled with UDPi™ (random) and unique for each processor. Importantly, UDPi™’s ability to scramble data does not rely on how many bits the micro has, resulting in advanced security for both 4-bit micros and more powerful devices alike.
The two options for the UDPiCore security method are a LFSR between the Instruction Register and Instruction Decoder or a simple XOR matrix. Data travels through UDPi™’s security block, corrupting opcode tables and scrambling data with the use of one chip.
UDPi™ provides security for processor IP. In addition to trusted control over communicating peripherals and protecting against sniffers attempting to access data traveling from one place to another, UDPi™ protects IP and data traveling within the micro itself.
UDPi™ does not require a separate chip for security functions, as the security functions funnel data through the UDPi™ flexible circuit block, providing internal silicon protection without the need for excessive mathematical number crunching. UDPi™ secures IP and the data traveling within the micro, creating true tamper-proof technology.
